1. Field of the Invention
The present invention relates to a circuit for reducing current consumption in a processor, and more particularly to a circuit for reducing current consumption by decreasing leakage current at a joint test action group (JTAG) test terminal.
2. Description of the Related Art
Processors are devices for controlling electronic apparatuses. Accordingly, they are essentially used in electronic apparatuses. These processors are used in various fields such as home electronics (e.g., computers, cell phones, and televisions as well as various transmission systems (e.g., base stations, base station controllers, and mobile exchange systems for a cell phone service).
Some electronic apparatuses are operated with only one processor. When an electronic apparatus is operated with one processor also known as a System On a Chip (SOC), the processor is provided with terminals for developing packaged programs and peripheral circuits.
Hereinafter, a chip such as an test mode select input (MSM) chip for use in mobile communication terminals, etc., and a chip from the Intel corporation will be described as an example.
The above-mentioned chip has a JTAG terminal for testing. Typically, the JTAG terminal includes five pins. Hereinafter, the pins will be described.
The first is a test clock input (TCK) pin to which a test clock signal is input, the second is a test reset input (hereinafter, referred to as a TRSTB) pin for performing a reset in a test operation, the third is a test data output (TDO) pin from which data are output in a test operation, the fourth is a test data input (TDI) pin to which data are input in a test operation, and the fifth is a TMS pin for placing the JTAG terminal in a test mode operation.
When developing a one chip printed circuit board, the JTAG terminal as described above is used for testing the printed circuit board, detecting a failure state of a chip, or monitoring an upgrade of a program to be tested in a product and the status of a program in operation.
A semiconductor chip supporting the JTAG test includes a tap controller. Further, the TRSTB pin (hereinafter, referred to as an initialization test terminal), which initializes the tap controller of the semiconductor chip supporting the JTAG test, maintains an initialization value using a pull up resistor on the inside of the chip for performing an initialization operation in the JTAG test. The pin is connected to initialize an operation of a processor in the chip in a normal operation mode of a system. Accordingly, referring to JTAG specification (ARM DDI 0029G) which is incorporated herein by reference and is a standard document for the JTAG terminal, after the power of the chip is turned on, the initialization test terminal maintains a low state (0) for an initial predetermined time and then is converted to a high state (1), or the initialization test terminal continuously maintains the low state from the beginning, so that the processor can operate normally.
Further, the initialization test terminal, which initializes the tap controller in the semiconductor chip used in constructing the system supporting the JTAG test, prevents a reset operation due to an exterior noise component from occurring by using the pull up resistor on the inside of the chip, similar to a general reset pin.
Further, the chip receives data and control signals through other pins of the JTAG terminal. For example, the data and control signals input as described above are output as data and control signals, which are converted to signals capable of being processed by the processor, from a JTAG interface circuit. That is, the data and control signals input from a test apparatus are input through each pin of the JTAG terminal, are processed by the JTAG interface circuit on the inside of the chip, and then are processed by the processor.
Meanwhile, since the JTAG terminal is used only when performing a test, or performing an upload or update of a program in the manufacture of a product, the JTAG terminal becomes useless once the product has been placed on the market That is, since the terminal does not perform special functions, the above-mentioned pins are generally mounted on the product in a floating state. Additionally, the initialization test terminal of the pins performs a reset operation and resets the processor. Accordingly, when the initialization test terminal maintains the floating state, noise is input due to variations in temperature, impact, static electricity, etc., and the processor may reset.
Hereinafter, the JTAG terminal will be described in more detail with reference to the graphs shown in FIGS. 1A and 1B. According to the graph shown in FIG. 1A, it is preferred that, a voltage waveform (marked by a thick line) of the initialization test terminal is initially maintained in the low state and then is converted to a high state after the power is turned on and after a power stabilization time point.
However, as described above, when the initialization test terminal is opened in the floating state, an unstable operation of the initialization test terminal may be caused by an offset voltage of an I/O pad due to a data cable (Uart voltage) or temperature variations when power is initially applied to the processor. Therefore, an abnormal operation such as ‘no booting’ may occur. That is, referring to FIG. 1B, the initialization test terminal (marked by a thick line) is converted to a high state prior to the power stabilization time point, thereby causing an abnormal operation.
Accordingly, in order to prevent the abnormal phenomenon from occurring, the existing circuit has a pull down resistor connected to the JTAG initialization test terminal, which enables the voltage of the initialization test terminal to be always maintained in the low state.
FIG. 2 is a diagram of a circuit formed when the pull down resistor is connected to the JTAG initialization test terminal according to the prior art.
Referring to FIG. 2, the pull down resistor 11 is connected to an exterior of the initialization test terminal 13 of the processor 10. In a normal mode, the pull down resistor 11 enables the voltage of the initialization test terminal 13 to be initially in a low state (0) for a processor initialization in the chip. Further, a pull up resistor 12 is in the processor chip 10 and is connected to the initialization test terminal 13. Accordingly, the initialization test terminal 13 receives a signal from a test apparatus in a JTAG test mode. That is, as shown in FIG. 3, the pull down resistor 11 enables the voltage (marked by a thick line) of the initialization test terminal 13 to remain in the low state (0), so that abnormal operation of the JTAG test terminal can be prevented.
Referring to FIG. 2, a reset chip 20 is connected to a reset terminal 14 of the processor 10, and the reset chip 20 applies a reset signal to the reset terminal 14. Specifically, when the power of the processor 10 is turned on, the reset chip 20 typically outputs the reset signal to the reset terminal 14 after the power is turned on and about 20 ms passes. A resistor 15 connected to the reset chip 20 is a pull up resistor for the reset terminal 14.
The reset chip 20 is always connected to the reset terminal 14 in order to reset the processor 10 as described above, and the initialization test terminal 13 and the reset terminal 14 generally maintain a floating state after a product has been produced.
Meanwhile, when the pull down resistor 11 and the pull up resistor 12 are disposed as described above, the product on which the processor is mounted has a current path formed between the pull up resistor 12 on the inside of the chip and the pull down resistor 11 on the exterior of the chip. That is, the processor always has a constant amount of leakage current through the current path. The leakage current can be obtained by the following equation 1 through a calculation based on FIG. 2, in which values of devices are employed in a modem chip in a general portable terminal as an example.                     I        =                              V            R                    =                                    2.8                              (                                                                            90                      ⁢                                                                                           ⁢                      K                                        ±                                          20                      ⁢                                                                                           ⁢                      K                                                        +                                      10                    ⁢                                                                                   ⁢                    K                                                  )                                      =                                          23                ~                35                            ⁢                                                           ⁢                              µ                ⁢                A                                                                        equation        ⁢                                   ⁢        1            
Herein, the pull up resistor 12 on the inside of the modem chip processor 10 has a theoretical value of 100K as shown in FIG. 2, but it has a value of 90K±20K in actuality.
That is, referring to equation 1, the modem chip processor 10 in the portable terminal always has unnecessarily consumed current of between 23 μA-35 μA through the initialization test terminal even though the processor is not being operated.
Accordingly, when the processor is operated by a battery, for instance, a mobile communication terminal or a notebook computer, the usage time of the product is shortened due to unnecessary leakage current even though the product is not being operated.